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| CMOS Static RAM 1 Meg (256K x 4-Bit) Features x x IDT71028 Description The IDT71028 is a 1,048,576-bit high-speed static RAM organized as 256K x 4. It is fabricated using IDT's high-perfomance, highreliability CMOS technology. This state-of-the-art technology, combined with innovative circuit design techniques, provides a costeffective solution for high-speed memory needs. The IDT71028 has an output enable pin which operates as fast as 6ns, with address access times as fast as 12ns. All bidirectional inputs and outputs of the IDT71028 are TTL-compatible and operation is from a single 5V supply. Fully static asynchronous circuitry is used, requiring no clocks or refresh for operation. The IDT71028 is packaged in a 28-pin 400 mil Plastic SOJ. x x x x 256K x 4 advanced high-speed CMOS static RAM Equal access and cycle times -- Commercial and Industrial: 12/15/20ns One Chip Select plus one Output Enable pin Bidirectional data inputs and outputs directly TTL-compatible Low power consumption via chip deselect Available in 400 mil Plastic SOJ package. Functional Block Diagram A0 * * * ADDRESS DECODER * * * 1,048,576-BIT MEMORY ARRAY A17 I/O0-I/O3 4 4 I/O CONTROL CS WE OE CONTROL LOGIC 2966 drw 01 FEBRUARY 2001 1 (c)2000 Integrated Device Technology, Inc. DSC-2966/08 IDT71028 CMOS Static RAM 1 Meg (256K x 4-Bit) Commercial and Industrial Temperature Ranges Pin Configuration A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 CS OE GND 1 28 27 2 3 26 25 4 24 5 23 6 SO28-6 22 7 21 8 9 20 10 19 11 18 17 12 13 16 15 14 VCC A17 A16 A15 A14 A13 A12 A11 NC I/O3 I/O2 I/O1 I/O0 WE Absolute Maximum Ratings(1) Symbol VTERM (2) TA TBIAS TSTG PT IOUT Rating Terminal Voltage with Respect to GND Operating Temperature Temperature Under Bias Storage Temperature Power Dissipation DC Output Current Value -0.5 to +7.0 0 to +70 -55 to +125 -55 to +125 1.25 50 Unit V o o o C C C W mA 2966 tbl 02 2966 drw 02 SOJ Top View NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed VCC + 0.5V. Capacitance Truth Table(1,2) CS L L L H VHC (3) (TA = +25C, f = 1.0MHz, SOJ package) Symbol I/O DATAOUT DATAIN High-Z High-Z High-Z Function Read Data Write Data Output Disabled Deselected - Standby (ISB) Deselected - Standby (ISB1) 2966 tbl 01 Parameter(1) Input Capacitance I/O Capacitance Conditions VIN = 3dV VOUT = 3dV Max. 8 8 Unit pF pF 2966 tbl 03 OE L X H X X WE H L H X X CIN CI/O NOTE: 1. This parameter is guaranteed by device characterization, but not production tested. NOTES: 1. H = VIH, L = VIL, x = Don't care. 2. VLC = 0.2V, VHC = VCC -0.2V. 3. Other inputs VHC or VLC. Recommended DC Operating Conditions Symbol VCC Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Min. 4.5 0 2.2 -0.5 (1) Typ. 5.0 0 ____ ____ Max. 5.5 0 VCC+0.5 0.8 Unit V V V V 2966 tbl 04 Recommended Operating Temperature and Supply Voltage Grade Commercial Industrial Temperature 0OC to +70OC -40OC to +85OC VSS 0V 0V VSS 5.0V 10% 5.0V 10% 2966 tbl 05 GND VIH VIL NOTE: 1. VIL (min.) = -1.5V for pulse width less than 10ns, once per cycle. 6.42 2 IDT71028 CMOS Static RAM 1 Meg (256K x 4-Bit) Commercial and Industrial Temperature Ranges DC Electrical Characteristics (VCC = 5.0V 10%, Commercial and Industrial Temperature Ranges) IDT71028 Symbol |ILI| |ILO| VOL VOH Parameter Input Leakage Current Output Leakage Current Output Low Voltage Output High Voltage Test Condition VCC = Max., VIN = GND to VCC VCC = Max., CS = VIH, VOUT = GND to VCC IOL = 8mA, VCC = Min. IOH = -4mA, VCC = Min. Min. ___ ___ ___ Max. 5 5 0.4 ___ Unit A A V V 2966 tbl 06 2.4 DC Electrical Characteristics(1) (VCC = 5.0V 10%, VLC = 0.2V, VHC = VCC - 0.2V) 71028S12 Symbol ICC Parameters Dynamic Operating Current, CS VIL, Outputs Open, VCC = Max., f = fMAX(2) Standby Power Supply Current (TTL Level) CS VIH, Outputs Open, VCC = Max., f=fMAX(2) Full Standby Power Supply Current (CMOS Level), CS VHC, Outputs Open, VCC = Max., f = 0(2), VIN VLC or VIN VHC Com'l. 155 Ind. 170 71028S15 Com'l. 150 Ind. 165 71028S20 Com'l. 145 Ind. 160 Unit mA ISB 40 40 40 40 40 40 mA ISB1 10 10 10 10 10 10 mA NOTES: 1. All values are maximum guaranteed values. 2. fMAX = 1/tRC (all address inputs are cycling at fMAX); f = 0 means no address input lines are changing. 2966 tbl 07 AC Test Conditions Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels AC Test Load GND to 3.0V 3ns 1.5V 1.5V See Figures 1 and 2 2966 tbl 08 AC Test Loads 5V 480 DATA OUT 30pF 255 2966 drw 03 5V 480 DATA OUT 5pF* 255 2966 drw 04 *Including jig and scope capacitance. Figure 2. AC Test Load Figure 1. AC Test Load 6.42 3 (for tCLZ, tOLZ, tCHZ, tOHZ, tOW, and tWHZ) IDT71028 CMOS Static RAM 1 Meg (256K x 4-Bit) Commercial and Industrial Temperature Ranges AC Electrical Characteristics (VCC = 5.0V 10%, Commercial and Industrial Temperature Ranges) 71028S12 Symbol Read Cycle tRC tAA tACS tCLZ (1) (1) 71028S15 Min. Max. 71028S20 Min. Max. Unit Parameter Min. Max. Read Cycle Time Address Access Time Chip Select Access Time Chip Select to Output in Low-Z Chip Deselect to Output in High-Z Output Enable to Output Valid Output Enable to Output in Low-Z Output Disable to Output in High-Z Output Hold from Address Change Chip Select to Power-Up Time Chip Deselect to Power-Down Time 12 -- -- 3 0 -- 0 0 4 0 -- -- 12 12 -- 6 6 -- 5 -- -- 12 15 -- -- 3 0 -- 0 0 4 0 -- -- 15 15 -- 7 7 -- 5 -- -- 15 20 -- -- 3 0 -- 0 0 4 0 -- -- 20 20 -- 8 8 -- 7 -- -- 20 ns ns ns ns ns ns ns ns ns ns ns tCHZ tOE tOLZ (1) tOHZ tOH tPU tPD (1) (1) (1) Write Cycle tWC tAW tCW tAS tWP tWR tDW tDH tOW (1) Write Cycle Time Address Valid to End-of-Write Chip Select to End-of-Write Address Set-Up Time Write Pulse Width Write Recovery Time Data Valid to End-of-Write Data Hold Time Output Active from End-of-Write Write Enable to Output in High-Z 12 10 10 0 10 0 7 0 3 0 -- -- -- -- -- -- -- -- -- 5 15 12 12 0 12 0 8 0 3 0 -- -- -- -- -- -- -- -- -- 5 20 15 15 0 15 0 9 0 4 0 -- -- -- -- -- -- -- -- -- 8 ns ns ns ns ns ns ns ns ns ns 2966 tbl 09 tWHZ(1) NOTE: 1. This parameter guaranteed with the AC load (Figure 2) by device characterization, but is not production tested. 6.42 4 IDT71028 CMOS Static RAM 1 Meg (256K x 4-Bit) Commercial and Industrial Temperature Ranges Timing Waveform of Read Cycle No. 1(1) tRC ADDRESS tAA OE tOE CS tOLZ (5) (5) (3) tACS tCLZ DATAOUT tCHZ (5) tOHZ (5) HIGH IMPEDANCE DATAOUT VALID tPD VCC SUPPLY ICC CURRENT ISB tPU 2966 drw 05 Timing Waveform of Read Cycle No. 2(1,2,4) tRC ADDRESS tAA tOH DATAOUT PREVIOUS DATAOUT VALID tOH DATAOUT VALID 2966 drw 06 NOTES: 1. WE is HIGH for Read Cycle. 2. Device is continuously selected, CS is LOW. 3. Address must be valid prior to or coincident with the later of CS transition LOW; otherwise tAA is the limiting parameter. 4. OE is LOW. 5. Transition is measured 200mV from steady state. 6.42 5 IDT71028 CMOS Static RAM 1 Meg (256K x 4-Bit) Commercial and Industrial Temperature Ranges Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)(1,2,4) tWC ADDRESS tAW CS tAS WE tWHZ DATAOUT (3) (6) tWP (2) tWR tOW HIGH IMPEDANCE tDW tDH (5) tCHZ (3) (5) DATAIN DATAIN VALID 2966 drw 07 Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)(1,4) tWC ADDRESS tAW CS tAS WE tDW DATAIN DATAIN VALID 2966 drw 08 tCW tWR tDH NOTES: 1. A write occurs during the overlap of a LOW CS and a LOW WE. 2. OE is continuously HIGH. If during a WE controlled write cycle OE is LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is as short as the specified tWP. 3. During this period, I/O pins are in the output state, and input signals must not be applied. 4. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state. 5. Transition is measured 200mV from steady state. 6.42 6 IDT71028 CMOS Static RAM 1 Meg (256K x 4-Bit) Commercial and Industrial Temperature Ranges Ordering Information IDT 71028 Device Type S Power XX Speed XX Package X Process/ Temperature Range Blank I Commercial (0C to +70C) Industrial (-40C to +85C) Y 400-mil Small Outline J-Bend (SO28-6) 12 15 20 Speed in nanoseconds 2966 drw 09 6.42 7 IDT71028 CMOS Static RAM 1 Meg (256K x 4-Bit) Commercial and Industrial Temperature Ranges Datasheet Document History 09/23/99: Pg. 1-4, 7 Pg. 1, 3, 4, 7 Pg. 6 Pg. 8 Pg. 3 Updated to new format Added industrial temperature range offerings Removed 17ns speed grade Revised notes and footnotes on Write Cycle No. 1 and No. 2 diagrams Added Datasheet Document History Revised ISB to accomidate speed functionality Not recommended for new designs Removed "Not recommended for new designs" 03/14/00 08/09/00 02/01/01 CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com for Tech Support: sramhelp@idt.com 800-544-7726, x4033 The IDT logo is a registered trademark of Integrated Device Technology, Inc. 6.42 8 |
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